High PSRR Low Drop-out Voltage Regulator (LDO)

In order to solve the stability problems and increase the PSRR performance of the Low Drop-out Voltage (LDO) a novel technique is presented. The main purpose of this work was to obtain a high PSRR, high power efficiency with a low load current. To achieve this, several techniques such as Nested Miller Compensation (NMC), Pole-Zero Tracking Frequency Compensation (PZTFC) and Single Miller Compensation (SMC) pole-splitting are used together to guarantee stability and dynamic biasing for a high PSRR at high frequencies. The LDO was simulated in SMIC 0.13μm CMOS technology, the results show that the LDO provides a full load transient response from 10 μA to 300 mA with a low drop-out voltage of less than 200 mV .